This invention relates in general to timer circuits and in particular to a two mode timer circuit that is capable of selectively generating two different duration output signals in response to a trigger pulse.
Timer circuits are well known in the art, especially in the digital field. They generally comprise monostable gates that are obtainable in an integrated circuit or "chip" form and which are used with external resistance-capacitance (RC) networks for timing control. Such timers are fairly precise in operation and may be readily procured at relatively low cost. Yet, there are many circuit applications where somewhat less precise timers would suffice. In some applications a timer having two selective time bases is required. In such applications the circuit of the invention will function at nearly the same degree of precision as a pair of monostable gates, but at about one-fifth the cost. The inventive dual mode timer uses a readily available low cost CMOS type 4001 chip that has four OR gates. Thus, the invention solves a need in the art for a low cost, simple dual mode timer of moderate precision.